Si5381/82 Multi-DSPLL Wireless Jitter Attenuator / Clock Multiplier with Ultra-Low Noise Rev E Data Sheet
●The Si5381/82 is an ultra high performance wireless jitter attenuator with multiple DSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) applications. The industry's first multi-PLL wireless jitter attenuator device is capable of replacing multiple discrete, high performance, VCXO-based jitter attenuators with a fully integrated single chip solution. The featured multi-PLL architecture supports timing paths for Ethernet and CPRI (Common Public Radio Interface) clock cleaning ,and generates any low-jitter, general-purpose clocks. The fixed frequency oscillator provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise.
●Applications:
■Wireless Infrastructure;
◆eCPRI RRH (Remote Radio Head);
◆BBU (Baseband Unit);
◆DU (Distribution Unit);
■Test and Measurement.
●KEY FEATURES:
■Supports simultaneous Ethernet, CPRI and general-purpose clocking in a single device;
■Input frequency range:
◆Differential: 8 kHz - 750 MHz;
◆LVCMOS: 8 kHz to 250 MHz;
■Output frequency range:
◆CPRI: up to 2.94912 GHz;
◆Other differential: up to 735 MHz;
◆LVCMOS: up to 250 MHz;
■Ultra-low RMS jitter:
◆72 fs typ (12 kHz–20 MHz);
■Phase noise of 122.88MHz carrier frequency:
◆-118 dBc/Hz @ 100Hz offset;
■ITU-T G.8262 compliant.
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Si5381 、 Si5382 、 Si5381A-E-GM 、 Si5382A-E-GM 、 Si5381A-E-EVB 、 Si5382A-E-EVB 、 Si538fg-Rxxxxx-GM 、 Si5381E-Exxxxx-GM |
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Multi-DSPLL Wireless Jitter Attenuator 、 Clock Multiplier with Ultra-Low Nois 、 ultra high performance wireless jitter attenuator 、 Evaluation Board |
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[ Wireless Infrastructure ][ eCPRI RRH ][ Remote Radio Head ][ BBU ][ Baseband Unit ][ DU ][ Distribution Unit ][ Test and Measurement ] |
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Datasheet |
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Please see the document for details |
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64-QFN |
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English Chinese Chinese and English Japanese |
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December 3, 2021 |
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Rev. 1.0 |
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2.6 MB |
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