Si5381/82 Rev. E Reference Manual
This Reference Manual is intended to provide system, PCB design, signal integrity, and software engineers the necessary technical information to successfully use the Si5381/82 devices in end applications. The official device specifications can be found in the Si5381/82 datasheet.
The Si5381/82 is a high performance jitter attenuating clock multiplier which integrates four/two any-frequency DSPLLs for applications that require maximum integration and in-dependent timing paths. A single low phase noise XO connected to the XA/XB input pins provides the reference for the device. The device supports ultra-low phase noise 4G/LTE clock generation and low jitter general-purpose clock synthesis from a single device.
Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on fourth generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs (4G/LTE frequency outputs). Each DSPLL supports independent Free Run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5381/82 is programmable via an SPI or I2C serial interface with in-circuit programmable non-volatile memory so that it always powers up in a known configuration.
●RELATED DOCUMENTS:
■Si5381/82 Data Sheet
■Si5381/82 Device Errata
■Si5381/82A-E-EVB User Guide
■Si5381/82A-E-EVB Schematics, BOM &Layout
■IBIS models
■JESD204B subclass 0 and subclass 1 support
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 2021 |
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Revision 1.1 |
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7.3 MB |
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