Si5381/82 Rev E Data Sheet

2020-07-23
The Si5381/82 is an ultra high performance wireless jitter attenuator with multipleDSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) ap-plications. The industry’s first multi-PLL wireless jitter attenuator device is capable ofreplacing multiple discrete, high performance, VCXO-based jitter attenuators with afully integrated single chip solution. The featured multi-PLL architecture supports tim-ing paths for Ethernet and CPRI (Common Public Radio Interface) clock cleaning ,and generates any low-jitter, general-purpose clocks. The fixed frequency oscillatorprovides frequency stability for free-run and holdover modes. This all-digital solutionprovides superior performance that is highly immune to external board disturbancessuch as power supply noise.

Silicon Labs

Si5381Si5382Si5381A-E-GMSi5382A-E-GMSi5381A-E-EVBSi5382A-E-EVBSi5381E-Exxxxx-GMSi538fg-Rxxxxx-GMSi5380Si5386Si534xSi538x

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Part#

Multi-DSPLL Wireless Jitter Attenuator / Clock Multiplier withUltra-Low NoiseEvaluation Board

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Wireless Infrastructure ]eCPRI RRH (Remote Radio Head) ]BBU (Baseband Unit) ]DU (Distribution Unit) ]Test and Measurement ]

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Datasheet

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ESD(HBM,2.0kV) 、 Pb-free 、 RoHS 6

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Please see the document for details

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QFN;64-QFN

English Chinese Chinese and English Japanese

February, 2020

Rev. 1.0

1.9 MB

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