Si5381/82 Rev. E Reference Manual
This Reference Manual is intended to provide system, PCB design, signal integrity, and software engineers the necessary technical information to successfully use the Si5381/82 devices in end applications. The official device specifications can be found in the Si5381/82 datasheet.
The Si5381/82 is a high performance jitter attenuating clock multiplier which integrates four/two any-frequency DSPLLs for applications that require maximum integration and independent timing paths. A single low phase noise XO connected to the XA/XB input pins provides the reference for the device. The device supports ultra-low phase noise 4G/LTE clock generation and low jitter general-purpose clock synthesis from a single device.Each DSPLL has access to any of the four inputs and can provide low jitter clocks on any of the device outputs. Based on fourth generation DSPLL technology, these devices provide any-frequency conversion with typical jitter performance under 100 fs (4G/LTE frequency outputs). Each DSPLL supports independent free-run, holdover modes of operation, as well as automatic and hitless input clock switching. The Si5381/82 is programmable via an SPI or I²C serial interface with in-circuit programmable non-volatilememory so that it always powers up in a known configuration.
RELATED DOCUMENTS：
●Si5381/82 Data Sheet
●Si5381/82 Device Errata
●Si5381/82A-E-EVB User Guide
●Si5381/82A-E-EVB Schematics, BOM &Layout
●IBIS models
●JESD204B subclass 0 and subclass 1suppor
The Si5381/82 integrates four/two independent any-frequency DSPLLs in a monolithic IC for applications that require a combination of 4G/LTE, wireline, and general-purpose clocking. Any clock input can be routed to any DSPLL. The output of any DSPLL can be routed to any of the device clock inputs. Based on 4th generation DSPLL technology, the Si5381/82 provides a clock-tree-on-a-chip solution for applications that need a mix of 4G/LTE and general-purpose frequencies.
DSPLL:
The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock frequency or freerun from the reference clock. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-low-phase-noise analog VCO, and a user configurable feedback divider. Use of an external XO provides the DSPLL with a stable lownoise clock source for frequency synthesis and for maintaining frequency accuracy in the Freerun or Holdover modes. No other external components are required for oscillation. A key feature of DSPLL is providing immunity to external noise coupling from power supplies and other uncontrolled noise sources that normally exist on printed circuit boards.The frequency configuration for each of the DSPLLs is programmable through the SPI or I²C interface and can also be stored in non-volatile memory. DSPLLB is primarily used to generate 4G/LTE frequencies. Fractional frequency multiplication (Mn/Md) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan are easily determined using the ClockBuilder Pro utility.
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Si5381 、 Si5382 、 Si5381A-E-EVB 、 Si5382A-E-EVB 、 Si538x-4x-EVB 、 Si5381A-E-EB |
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[ applications that require maximum integration and in-dependent timing paths ][ applications that need a mix of 4G/LTE and general-purpose frequencies ][ high-performance, fully-integrated JEDEC JESD204B jitter cleaner ] |
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User's Guide |
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Please see the document for details |
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64-Pin QFN |
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English Chinese Chinese and English Japanese |
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May 2019 |
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Rev. 1.0 |
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6.5 MB |
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