Si5381/82 Data Sheet

PublishTime：2019-05-25

The Si5381/82is a wireless multi-PLL, jitter-attenuating clock that leverages SiliconLabs’ latest fourth-generation DSPLL technology to address the form factor, power, andperformance requirements demanded by radio area network equipment, such as smallcells, baseband units, and distributed antenna systems (DAS). The Si538x is the indus-try’s first multi-PLL wireless clock generator family capable of replacing discrete, high-performance, VCXO-based clocks with a fully integrated CMOS IC solution. TheSi5381/82features a multi-PLL architecture that supports independent timing paths forJESD wireless clocks with less than 85 fs typical phase jitter as well as Ethernet and oth-er low-jitter, general-purpose clocks. DSPLL technology also supports free-run and hold-over operation as well as automatic and hitless input clock switching. This unparalleledintegration reduces power and size without compromising the stringent performance andreliability demanded in wireless applications.

Brand of Product：	Silicon Labs
Part#：	Si5381 、 Si5382 、 Si5381A-E-GM 、 Si5382A-E-GM 、 Si5381E-E-GM 、 Si5382E-E-GM 、 Si5381E-E-EVB 、 Si5382E-E-EVB 、 Si538fg-Rxxxxx-GM 、 Si5381E-Exxxxx-GM 、 Si5381A 、 Si5382A 、 Si5381E 、 Si5382E 、 Si5381g-Rxxxxx-GM 、 Si5382g-Rxxxxx-GM More Part#
Product Category：	Multi-DSPLL Wireless Jitter Attenuating Clocks 、 Evaluation Board More
Application：	[ Pico cells, small cells ][ Mobile backhaul ][ Multiservice Distributed Access Systems (MDAS) ] More
Data Type：	Datasheet More
Safety & Environment Standards：	ESD(HBM,2KV) 、 IPC-7351 、 JEDEC J-STD-020 、 JEDEC/IPC J-STD-020 、 JESD204B 、 JESD78 、 Pb-Free 、 RoHS-6 More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：	64-Lead9x9 mmQFN
Language：	English Chinese Chinese and English Japanese
Date of Creation：	September 25, 2017
Version Number：	Rev. 0.9
Data Encoding：
Data Size：	1.5 MB

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