Si5381/82 Evaluation Board User's Guide
The Si5381/82A-E-EB is used for evaluating the Ultra-Low Phase Noise Quad/Dual PLL. The Si5381/82 employs fourth-generation DSPLL technology to enable clock generation for LTE/ JESD204B applications which require the highest level of jitter performance. The Si5381/82A-E-EB has four independent input clocks and a total of 12 outputs with 4/2 PLLs. The Si5381/82A-E-EB also has four independent input clocks and a total of 12 outputs with 2 PLLs. The Si5381/82A-E-EB can be easily controlled and configured using Silicon Labs’ Clock Builder Pro™ (CBPro™) software tool.
The device revision is distinguished by a white 1 inch x 0.187 inch label with the text“Si5381/82A-E-EB” installed in the lower left hand corner of the board.
Powered from USB port or external powersupply;Onboard 54 MHz XO provides holdovermode of operation on the Si5381/82;CBPro GUI programmable VDDO suppliesallow each of the ten primary outputs tohave its own supply voltage selectablefrom 3.3, 2.5, or 1.8 V;CBPro GUI-controlled voltage, current,and power measurements of VDD and allVDDO supplies;Status LEDs for power supplies andcontrol/status signals of Si5381/82;SMA connectors for input clocks andoutput clocks
Si5381 、 Si5382 、 Si5381A-E-EB 、 Si5382A-E-EB 、 Si5381A 、 Si5381B 、 C8051F380 、 Si5382A |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2018/05/03 |
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Rev. 1.1 |
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16.8 MB |
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