Si5381/82 Data Sheet
DSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) applications.
The industry’s first multi-PLL wireless jitter attenuator device is capable of
replacing multiple discrete, high performance, VCXO-based jitter attenuators with a
fully integrated single chip solution. The featured multi-PLL architecture supports independent
timing paths for Ethernet and CPRI (Common Public Radio Interface)
clock cleaning , and generates any low-jitter, general-purpose clocks. The fixed frequency
oscillator provides frequency stability for free-run and holdover modes. This
all-digital solution provides superior performance that is highly immune to external
board disturbances such as power supply noise.
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Si5381 、 Si5382 、 Si5381A-E-GM 、 Si5382A-E-GM 、 Si5381A-E-EVB 、 Si5382A-E-EVB 、 Si5381E-Exxxxx-GM 、 Si538fg-Rxxxxx-GM 、 Si534x 、 Si538x 、 Si5380 、 Si5386 |
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Multi-DSPLL Wireless Jitter Attenuator / Clock Multiplier with Ultra-Low Noise 、 Evaluation Board |
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[ Wireless Infrastructure ][ eCPRI RRH (Remote Radio Head) ][ BBU (Baseband Unit) ][ DU (Distribution Unit) ][ Test and Measurement ] |
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Datasheet |
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Pb-free 、 RoHS |
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Please see the document for details |
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64-QFN |
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English Chinese Chinese and English Japanese |
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April, 2019 |
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Rev. 0.96 |
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1.8 MB |
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