Lattice Sentry PLD Interface IP Core -Lattice Propel Builder User Guide
■The Lattice Semiconductor Customer Programmable Logic Device(PLD) Interface IP implements a register interface, which is used by firmware to send and receive messages to and from the customer's control PLD logic to request system control actions and check status. This user guide defines the hardware and register interface for the firmware and the hardware interface to the customer's logic.
●Features
■The key features of the Lattice Sentry Customer PLD IP are:
▲Implements a bidirectional mailbox mechanism for sending small(8-bit) messages to the customer PLD logic and receiving messages from the customer PLD logic
▲Supports either AMBA 3 APB Protocol v1.0 or AHB-lite Protocol for CPU access
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MachXO2 、 MachXO3 、 MachXO3D 、 Mach-NX 、 CrossLink-NX 、 Certus-NX |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 2021 |
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Revision 1.2 |
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FPGA-IPUG-02106-1.2 |
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808 KB |
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