Memory Usage Guide for MachXO2 Devices Technical Note
■This technical note discusses the memory usage for the Lattice MachXO2™ PLD family. It is intended to be used by design engineers as a guide in integrating the EBR and PFU based memories for these devices in is pLEVER®.
■The architecture of these devices provides resources for memory intensive applications. The sysMEM™ Embedded Block RAM (EBR) complements the distributed PFU-based memory. Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM, FIFO and ROM memories can be constructed using the EBR. LUTs and PFU can implement Distributed Single-Port RAM, Dual-Port RAM and ROM.
■The capabilities of the EBR Block RAM and PFU RAM are referred to as primitives and are described later in this document. You can utilize the memory primitives in two ways:
▲Via IPexpress™ –The IPexpress user interface allows you to specify the memory type and size that is required. IPexpress takes this specification and constructs a netlist to implement the desired memory by using one or more of the memory primitives.
▲Via the PMI (Parameterizable Module Instantiation)–PMI allows experienced users to skip the graphical interface and utilize the configurable memory modules on the fly from the is pLEVER Project Navigator. The parameters and the control signals needed either in Verilog or VHDL can be set. The top-level design has the parameters defined and signals declared so the interface can automatically generate the black box during synthesis.
■In addition to familiar Block RAM and PFU RAM primatives, MachXO2-640 and higher density devices provide a new User Flash Memory (UFM) block, which can be used for a variety of applications including storing a portion of the configuration image, storing and initializing EBR data, storing PROM data or as a general purpose non-volatile user Flash memory. The UFM block connects to the device core through the embedded function block WISHBONE interface. You can also access the UFM block through the JTAG, I²C and SPI interfaces of the device. The UFM block offers the following features:
▲Non-volatile storage up to 256 Kbits
▲Byte addressable for read access. Write access is performed in 128-byte pages.
▲Program, erase, and busy signals
▲Auto-increment addressing
▲WISHBONE interface
▲External access is provided through JTAG, I²C,and SPI interfaces
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MachXO2 、 MachXO2-1200 、 MachXO2-4000 、 MachXO2-640 、 MachXO2-256 |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 2020 |
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Revision 1.4 |
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FPGA-TN-02159-1.4 |
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4.7 MB |
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