Implementing High-Speed Interfaces with MachXO2 Devices Technical Note
■In response to the increasing need for higher data bandwidth, the industry has migrated from the traditional Single Data Rate (SDR) to the Double Data Rate (DDR) architecture. SDR uses either the rising edge or the falling edge of the clock signal to transfer data, while DDR uses both edges of the clock signal for data transfer. This essentially doubles the data transmission rate using the same clock frequency because the data is transferred twice per clock cycle. The DDR clocking technique has largely been used in memory interfaces such as DDR SDRAM. As are sult, DDR SDRAM memories achieve twice the bandwidth as SDR SDRAM memories without increasing the signal integrity requirements in the system.
■The Lattice MachXO2™ PLD family supports high-speed interfaces for both DDR and SDR applications through built-in Programmable I/O (PIO) logic. The MachXO2 devices also have dedicated circuitry to support DDR, DDR2, and LPDDR SDRAM memory interfaces. This document focuses on the implementation of high-speed generic DDR interfaces, and memory DDR/DDR2 and LPDDR interfaces in the MachXO2 devices. It also provides guidelines for making use of the built-in capabilities of the MachXO2 devices to achieve the best performance for high speed interfaces.
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MachXO2 、 MachXO2-640U 、 MachXO2-1200/U 、 MachXO2-2000 、 MachXO2-2000U 、 MachXO2-4000 、 MachXO2-7000 |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 2020 |
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Revision 1.8 |
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FPGA-TN-02153-1.8 |
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2.3 MB |
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