MachXO2 SED Usage Guide Technical Note
■Memory errors can occur when high-energy charged particles alter the stored charge in a memory cell in an electronic circuit. The phenomenon first became an issue in DRAM, requiring error detection and correction for large memory systems in high-reliability applications. As device geometries have continued to shrink, the probability of memory errors in SRAM has become significant for some systems. Designers are using a variety of approaches to minimize the effects of memory errors on system behavior.
■SRAM-based PLDs store logic configuration data in SRAM cells. As the number and density of SRAM cells in an PLD increase, the probability that a memory error will alter the programmed logical behavior of the system increases. A number of approaches have been taken to address this issue, but most involve Intellectual Property (IP) cores that the user instantiates into the logic of their design, using valuable resources and possibly affecting design performance. The MachXO2™ devices have a hardware implemented SED circuit which can be used to detect SRAM errors and allow them to be corrected.
■This document describes the hardware-based SRAM CRC Error Detect (SED) approach taken by Lattice Semiconductor for MachXO2 PLDs.
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MachXO2 、 MachXO2-256 、 MachXO2-640 、 MachXO2-640U 、 MachXO2-1200 、 MachXO2-1200U 、 MachXO2-2000 、 MachXO2-2000U 、 MachXO2-4000 、 MachXO2-7000 |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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November 2019 |
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Revision 2.1 |
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FPGA-TN-02156-2.1 |
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709 KB |
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