MachXO2 sysCLOCK PLL Design and Usage Guide Technical Note
■The MachXO2™ devices support a variety of I/O interfaces such as display interfaces (7:1 LVDS) and memory interfaces(LPDDR, DDR, DDR2). In order to support applications which use these interfaces, the MachXO2 device architecture has been designed to include advanced clocking features that are typically found in higher density FPGAs. These features provided designers the ability to synthesize clocks, minimize clock skew, improve performance and manage power consumption.
■This technical note describes the clock resources available in the MachXO2 devices. Details are provided for primary clocks, edge clocks, clock dividers, sysCLOCK™ PLLs, DCC elements, the secondary high fan-out nets, and the internal oscillator available in the MachXO2 device.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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September 2021 |
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Revision 2.9 |
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NoteFPGA-TN-02157-2.9 |
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1.5 MB |
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