MachXO2 Soft I2C Slave with Clock Stretching Reference Design User Guide
■The primary purpose of this Reference Design is to provide a form, fit and function equivalent, “drop-in” module to replace the Lattice MachXO2 hard I²C core in user designs which require Clock-Stretching support. This reference design has been engineered to require little or no modification to pre-existing WISHBONE bus control logic, and to provide pin-for-pin hook-up. The reference design utilizes ‘soft’ LUT resources instead of ‘hard’ logic. As this design consumes additional fabric resources, it can impact timing closure and/or design routability is certain designs. Please refer to Port List, Register Definitions, and Resource Utilization sections for more details.
■I²C Clock-Stretching is an optional flow-control mechanism in the I2C specification. A slave device can use clockstretching to force a pause in an I²C transaction by holding the SCL line low (‘0’). The I²C Master is prevented from continuing the transaction until the slave releases SCL. The MachXO2 hard I2C block does not operate reliably when clock-stretching is enabled. See References section for additional information on I²C bus operation.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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November 2019 |
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Revision 1.2 |
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FPGA-RD-02092-1.2 |
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1.1 MB |
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