Lattice Sentry QSPI Monitor IP Core for MachXO3D -Lattice Propel Builder User Guide
■A Quad-Serial Peripheral Interface (QSPI) is a serial interface where in four data lines are used to read, write,and erase flash chips. It is faster than the traditional Serial Peripheral Interface (SPI) and is specifically designed to communicate with flash chips that support this interface. Unlike the traditional SPI that uses separate data lines for input and output (MISO and MOSI), the QSPI interface configures the data lines on the fly to act as outputs to send some information to the flash memory and act as inputs to read some memory contents.
■The Lattice Semiconductor Sentry™QSPI Monitor for MachXO3D™ is a security module that can monitor SPI or QSPI buses. The design is implemented in Verilog HDL. It can be configured and generated using Lattice Propel™Builder. It can be targeted to MachXO3D FPGA devices and implemented using the Latttice Diamond® software Place and Route tool integrated with the Synplify Pro® synthesis tool.
●Features
■The key features of the QSPI Monitor IP are:
▲Supports up to five external SPI/QSPI buses to monitor illegal activity
▲Enable/disable dynamically the flash initialization commands per monitor
▲Flash commands (program, read, erase) are monitored based on address ranges
▲Supports up to four dynamically configurable address ranges for filtering per monitor
▲Supports both 24-bit and 32-bit flash addressing modes/commands
▲AMBA 3 APB Protocol v1.0
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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May 2020 |
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Revision 1.0 |
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FPGA-IPUG-02110-1.0 |
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951 KB |
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