Lattice Sentry QSPI Master Streamer IP Core for MachXO3D -Lattice Propel Builder User Guide
■A Quad-Serial Peripheral Interface (QSPI) is a serial interface, where four data lines are used to read, write,and erase flash chips. It is faster than the traditional Serial Peripheral Interface (SPI) and is specifically designed to communicate with flash chips that support this interface. Unlike the traditional SPI that uses separate data lines for input and output (MISO and MOSI), the QSPI interface configures the data lines on the fly so that they act as outputs to send some information to the flash memory and act as inputs to read some memory contents.
■The Lattice Semiconductor Sentry™ QSPI Master Streamer IP core for MachXO3D™ supports SPI and QSPI transactions. The design is implemented in Verilog HDL. It can be configured and generated using Lattice Propel™ Builder. It can be targeted to MachXO3D™ FPGA devices and implemented using the Lattice Diamond® software Place and Route tool integrated with the Synplify Pro® synthesis tool.
●Features
■The key features of the QSPI Master Streamer IP include:
▲Generation of SPI and QSPI transactions
▲Support for long SPI transactions (up to 256 byte write and 4 Gb read) with no CPU interactions
▲Programmable transaction type and length
▲Provision of external 8-bit FIFO interface for connecting to other blocks
▲Support for AMBA 3 APB Protocol v1.0
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