Miller Effect on MOS Tube Switches

PublishTime： 2024-02-09 Article Source：HI-SEMICON News

The basic principle of formation of Miller platform

The gate drive process of MOSFET can be simply understood as the charging and discharging process of the input capacitance (mainly C_GS of the gate source capacitance) of the MOSFET. When THE C_GS reaches the threshold voltage, MOSFET will enter the opening state. When MOSFET is opened, V_DS starts to decline and ID starts to rise. At this time, MOSFET enters the saturated region. However, due to Miller effect, V_GS will not rise for a period of time. At this time, I_D has reached the maximum, while V_DS continues to decline until Miller capacitor is fully charged and V_GS rises to the value of the driving voltage. At this time, MOSFET enters the resistance area, V_DS completely drops and the opening ends.

Because miller capacitors prevent V_GSfrom rising, they prevent Vds from falling, thus increasing the time to wear out. (When V_GS goes up, the conduction resistance goes down, thus V_DS goes down)

Fig.1

Miller effect is notorious in MOS drive. It is caused by the miller capacitance of the MOS tube. During the opening process of the MOS tube, the G_S voltage rises to a certain voltage value and then becomes stable for some time, after which the G_S voltage starts to rise again until complete conduction. Why is there a stable value here? Before the MOS is switched on, the D-pole voltage is greater than the G-pole voltage, and the electric quantity stored by the MOS parasitic capacitor C_GD needs to be neutralized by the G pole injected during its conduction because the G-pole voltage is greater than the D-pole voltage after the MOS is fully switched on. The Miller effect will greatly increase the opening loss of MOS. (The MOS tube cannot be switched on very quickly)

So there comes the so-called totem drive!! When MOS is selected, the smaller the C_GD is, the smaller the switching loss will be. The Miller effect is unlikely to disappear entirely.

Miller platform in MOSFET is a typical symbol of MOSFET being in the "big zone".

Using an oscilloscope to measure the G_S voltage, you can see that there is a platform or pit during the voltage rise, this is the Miller platform.

The detailed process of formation of the Miller platform
The Miller effect refers to the miller platform produced in the opening process of the MOS tube switches. The principle is as follows.

In theory, the Miller effect can be eliminated by adding enough capacitance between the G and S stages of the drive circuit. But the switching time will drag on for a long time. The general recommendation plus a capacitance value of 0.1C_IESS is beneficial.

The gentle part in the thick black line below is the Miller platform.

Fig.2

This diagram shows the delay-charge coefficient at the first turning point: V_DS starts conduction. The variation of V_DS forms a differential through C_GD and the internal resistance of the driver source. Since V_DS is approximately linearly decreasing, linear differentiation is a constant, resulting in a platform at V_GS.

Miller platform is caused by the capacitance at both ends of MOS G_D, namely C_RSS in the MOS datasheet.

This process is to charge THE C_GD, so the V_GS changes very little. When the C_GD is charged to the V_GS level, the V_GS will continue to rise.

When MOS was just opened, C_GD discharged rapidly through MOS, and then the drive voltage was reversed charged, which Shared the drive current, making the voltage rise on C_GS slow and the platform appeared.

Fig.3

T0 ~ T1: V_GS from 0 to V_THMosfet not through Current by parasitic diode D_F
T1 ~ T2: V_GS from V_TH to Va I_D
T2 ~ T3: V_DS decreases, The higher the current continues to pass through C_GDV_DD, the longer the time required.

I_G is the driving current

It starts to get healthier faster When V_DG approaches zero, C_GD increases Until V_DG becomes negative, C_GD increases to the maximum IG decreases slowly

T3 ~ T4: complete conduction of Mosfet, operating in resistance zone V_GS continues to rise to V_GG

Fig.4

In the later stage of the platform, V_GS continued to grow, and I_DS changed little because MOS was saturated. However, from the picture of the building owner, this platform still had a length

During this platform, it can be considered that MOS is in the amplification period

Before the previous inflection point: MOS cutoff period, at which time C_GS is charging and V_GS is pressing into V_TH
The previous inflection point: MOS officially entered the amplification period

At the latter inflection point, MOS officially exits the amplification period and begins to enter the saturation period

When a voltage V with a slope of it is applied to capacitance C (such as the output voltage of the driver), the current in the capacitor will be increased:
I = C x dV/dt (1)
Therefore, when voltage is applied to MOSFET, input current I_GATE = I1 + I2 will be generated, as shown in the figure below:

Fig.5

Using Equation (1) on the right voltage node, the following equation can be obtained:

I1 = C_GD x d (V_GS - V_DS)/dt = C_GD x (dVgs/dt - dVds/dt) (2)
I2 = C_GS x d (V_GS/dt) (3)

If the grid-source voltage V_GS is applied to the MOSFET, the leak-source voltage V_DS will drop (even in a non-linear fashion). Therefore, the negative gain of connecting the two voltages can be defined as:

Av= -V_DS/V_GS (4).

Substituting Equation (4) into Equation (2), we can get:

I1=C_GD× (1+Av) dVgs/dt (5)

In the conversion (conduction or turn-off) process, the total equivalent capacitance Ceq of the grid-source electrode is:

I_GATE = I1 + I2 = (C_GD x (1 + Av) + C_GS) * dVgs yet dVgs/dt = Ceq/dt (6)

The term (1+Av) is called the Miller effect, which describes the capacitive feedback between output and input in an electronic device. The Miller effect occurs when the grid-drain voltage is close to zero.

C_DS diverts the most severe stage in a large area. Why? Because V_D changes the most dramatically at this stage. It is precisely at this stage that the platform is formed. You can assume that the gate current I_GATE is completely absorbed by the C_DS and no current flows to the C_GS.

Fig.6

Note the representation in the datasheet:

C_ISS=C_GS+C_GD

C_OSS=C_DS+C_GD

C_RSS=C_GD

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