IMP16C552 Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
■The low power COMS IMP16C522 is a single device solution for serving two serial input/output ports simultaneously and one fully bi-directional parallel port for the IBM PC ATM PS/2 and compatible systems. The parallel port is full compatible to the Centronics printer port and IBM serial parallel Adapter. Each Universal Asynchronous Receiver and transmitter (UART) is fully programmable. Each UART in the IMP16C522 is capable of buffering up to 16 bytes of data upon reception, relieving the CPU of interrupt overhead. Buffering of data also allows greater latency time in interrupt servicing which is vital in a multitasking environment, DMA signaling between the internal FIFO buffers and host CPU allows single or multiple character transfers. Each UART has a maximum recommended data rate of 256k with a clock frequency of 80MHZ
●General Description
■The IMP16C552 is an enhanced dual channel version of the IMP16C550A Universal Asynchronous Receiver and Transmitter (UART) plus a bi-directional parallel data port which fully support a Centronics compatible printer interface
■The two serial input/output Universal Asynchronous Receiver/Transmitter interface simultaneously in microprocessor-based system. Each UART performs parallel-to-serial conversion on the output and serial-to parallel conversion on the input. Two modes of operation exits for each I/0 channel after a hardware reset. Each UART is functionally compatible to the IMP16C450(character mode)and an alternate mode (FIFO mode)which is only available on the IMP16C552 It can be activated through software relieving the CPU of excessive overhead due to due to interrupts. The complete status of each UART can be read at any time from internal registers. The parallel port allows information received from the data base to be printed. The parallel port together with the two serial ports, provides IBM PC ATM and PS/2tm compatible with a single device solution.
●Key Features
■Two fully programmable serial 1/0 channels (DC TO 512K BAUD )
■Tri-state TTL drive capabilities for bi-directional data bus and control bus on each channel
■Loopback control for communications link fault isolation for each UART
■Line break generation and detection for each UART
■Complete status reporting capabilities
■Generation and stripping of serial asynchronous data control bits (start ,stop parity )
■Programmable baud rate generator and modem control signals for each channel
■Fully prioritized independent interrupt system controls for each channel
■16byte FIFO buffers on both transmit and receive of each channel to reduce number of interrupts presented to the CPU
■Programmable FIFO threshold loves of 1,4,8,or 14,bytes on each channel
■Two modes of DMA signaling available for transfer of data characters to and from FIFO buffers
■Fully bi-directional centronics compatible parallel port direct printer interface
■Advanced CMOS low power technology with single +5voit supply
■68-pin PLCC package
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Datasheet |
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Please see the document for details |
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PLCC |
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English Chinese Chinese and English Japanese |
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08/08/05 |
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Revision:A |
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4.5 MB |
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