Platform Manager 2 and L-ASC10 Datasheet Update (08A-19)
■Lattice Semiconductor is providing this notification of changes to the Platform ManagerTM2 and L-ASC10 Data Sheets.
■This PCN covers two distinct changes to the Platform Manager 2 family.
●Change #1 Description
●The Platform Manager 2 Data Sheet (FPGA-DS-02036 Version 2.3, released in September 2019) and L-ASC10 Data Sheet (FPGA-DS-02038 Version 2.1, released in September 2019) have updated R-addr values for the 6thand 7th device. The R-addr resistor is connected from ground to the I²C_ADDR pin(pin 16 of the L-ASC10 and ball K6 of the LPTM21L 100-Ball caBGA). The function of the I²C_ADDR pin is to set the lower three bits of Analog Section's I2C address at power up. This is to support multiple devices on the same I²C chain
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L-ASC10-1SG48I 、 LPTM21L-1ABG100I 、 LPTM21-1AFTG237C 、 LPTM21-1AFTG237 、 L-ASC10 |
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PCN/EOL |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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September 30, 2019 |
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08A-19 |
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285 KB |
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