Adding Scalable Power and Thermal Management to MachXO2 and MachXO3 Using L-ASC10 Application Note
■Complex hardware systems require a large number of resources for sensing analog signals, programmable digital control and many GPIOs to provide interface with external components. It is desired to have a flexible system where above resources can be easily scaled as per application requirement. Lattice Platform Manager™ 2 family consists of Hardware Management Expander (L-ASC10), which in combination with hardware management controller, MachXO2™, MachXO3™, and ECP5™ FPGAs enable designers to create a flexible and scalable hardware system.
■Lattice Diamond® software includes the Platform Designer tool which is used to configure L-ASC10 and MachXO2, MachXO3, or ECP5 FPGA. The tool also provides a mechanism to set up the interface between L-ASC10 and the controlling FPGA. With the help of the Platform designer tool, the user can easily build solutions for Voltage, Current, Temperature monitoring, fault-logging, hot-swap, trimming and margining, power supply sequencing and supervision by adding L-ASC10 to a MachXO2, MachXO3, or ECP5 design.
■This document explains the procedure to add L-ASC10 device to new or existing MachXO2 and MachXO3 designs. It describes the Platform Designer tool settings and external hardware connections to construct a system having power and thermal management using MachXO2 or MachXO3 and L-ASC10 devices. For details on adding L-ASC10 devices to new or existing ECP5 designs, please refer to AN6095, Adding Scalable Power and Thermal Management to ECP5 Using L-ASC10.
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L-ASC10 、 ECP5 、 MachXO2 、 MachXO3 、 LCMXO2-640 、 LCMXO2-1200 、 LCMXO2-2000 、 LCMXO2-4000 、 LCMXO2-7000 、 LCMXO3LF-640LF 、 LCMXO3LF-2100LF 、 LCMXO3LF-1300LF 、 LCMXO3LF-4300LF 、 LCMXO3LF-6900LF 、 LCMXO3LF-9400LF 、 MachXO2 family 、 MachXO3 family 、 LCMXO2-1200HC |
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Hardware Management Expander 、 hardware management controller 、 FPGA |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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October 2019 |
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Version 1.2 |
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FPGA-AN-02011 |
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2.1 MB |
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