LL10GEMAC IP Demo Instruction

PublishTime：2022-04-29

●This document describes the instruction to run loop back demo on FPGA development board. The demo is designed to run LL10GEMAC IP loop back test for measuring the latency time.User sets test parameter on FPGA board and monitors the hardware status via Serial console.More details of the demo are described as follows.

Brand of Product：	Design Gateway
Part#：	LL10GEMAC IP 、 LL10GEMAC More Part#
Product Category：	IP core More
Application：	More
Data Type：	User's Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	21-May-20
Version Number：	Rev1.0
Data Encoding：
Data Size：	866 KB

Data section preview(2pages)

- The full preview is over. If you want to read the whole 7 page document,please Sign in/Register -

Download

+1 Like
Add to Favorites

Recommend

Technical Resources

More>

All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.

Integrated Circuits