LL10GEMAC IP Core
■10 Gbps Ethernet MAC and PCS
■Directly connecting with Intel transceiver PHY (PMA) by 32-bit interface
■Low latency solution: 65.1 ns for round-trip latency (18.6 ns for Tx path. 21.7 ns for Rx path, and 24.8 ns for PMA latency)
■AvaIon-stream interface with the user logic
■Small resource utilization
■Minimum Tx packet size: 5 bytes
■FCS (CRC-32) inserting and checking
■64B/66B Encoding and Decoding following IEEE802.3ae specification
■Supporting 10GBASE-R standard
■Appe riding zero padding for Tx in terface. but not rem oving zero paddi ng for Rx interface
■In dividual clock domain for transmit and receive in terface at 322.265625 MHz
■Reference design available on Intel development board (ArrialO GX)
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[ Nowadays the network with low latency access is the core for many real-time applications such as High Frequency Trading (HFT) ][ Data center ][ and Real-time control system in Industrial and Automotive ][ LL10GEMAC is designed to implement Ethernet MAC and PCS for low latency networking by 10Gb Ethernet ][ The example application of HFT by using LL10GEMAC is shown in Figure 1 ] |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 26,2021 |
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Rev1.0 |
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589 KB |
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