Design Gateway’s Low Latency Networking IP

PublishTime：2022-04-29

●Design Gateway’s Low Latency Networking IP is designed from the ground up for very low latency requirements.
■Highly integrated and optimized
▲We have designed and optimized both TCP/UDP full offload engine IP and also EMAC+PCS IP for FPGA transceiver. to achieve very low latency, very high speed, low FPGA resources.

Brand of Product：	Design Gateway
Part#：	LL 10GEMAC IP 、 UDP10GRx-IP 、 LL10GEMAC IP 、 UDP10GTx-IP 、 TOE10GLL-IP 、 10GEMAC-IP 、 UDP10G Rx/Tx-IP 、 TOE10G-IP More Part#
Product Category：	Low Latency Networking IP 、 Networking IP core More
Application：	[ FinTech applications ][ HFT ][ Market Data Processing ][ Tick-to-Trade systems. ] More
Data Type：	Technical Documentation More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	2020/4/23
Version Number：
Data Encoding：
Data Size：	1 MB

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