LL10GEMAC-IP reference design

PublishTime：2021-08-10

●The application layer, transport layer, and network layer of Ethernet system in FPGA are mostly implemented by the CPU software for system flexibility. The Link and Physical layer can be designed by using 10G EMAC and 10G BASE-R PHY which are Intel IP core. In some applications which are very sensitive about data latency such as HFT (High Frequency Trading), using CPU system shows too much latencytime because of software-hardware handling process.
●To achieve the lowest latency time, pure hardwired logic is purposed. As shown in the right side of Figure 1-1, the low-level protocol is designed by using LL10GEMAC-IP operating with 10GbE PMA. Moreover, the high-level protocols such as TCP/IP and UDP/IP can be implemented by pure-hardwired logic such as TOE10GLL-IP, UDP10GTx-IP, and UDP10GRx-IP. By using all hardwired logic solution, user can design simple logic for transfening the data via 10Gb Ethernet system with achieving very low latencytime.
●LL10GEMAC-IP consists of EMAC and PCS logic (the top part of Physical layer) while PMA logic (the low part of Physical layer) is implemented by using Intel Transceiver.

Brand of Product：	Design Gateway
Part#：	LL10GEMAC-IP More Part#
Product Category：	More
Application：	More
Data Type：	Application note & Design Guide More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	26-Mar-21
Version Number：	Rev1.0
Data Encoding：
Data Size：	709 KB

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