FPGA Setup for LL10GEMAC-IP Loopback Test

2021-08-10
●This document describes howto setup FPGA board and prepare the test environment for running LL10GEMAC-IP loopback demo and measuring the latency time. User sets test parameters on FPGA board and monitors the hardware status via Serial console. More details of the demo are described as follows.

Design Gateway

LL10GEMAC-IP

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Part#

FPGA board

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Technical Documentation

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Please see the document for details

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29-Apr-21

Rev1.0

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