LL10GEMAC IP Core Product Specification
■LL10GEMAC IP implements the MAC layer and the PCS (Physical Coding Sublayer) layer for 10Gb Ethernet solution. After power up, Rx interface of 10GbE PMA (Physical Medium Attachment) must be calibrated by Synchronization until the received data is locked. Next, Rx Controller monitors the received data from 10GbE PMA to check link up status of 10GbE. When the connection is ready, LL10GEMAC IP asserts ready signal to user interface. So, the user can transmit the packet to LL10GEMAC IP.
■For transmitting the packet, the preamble and SFD (Start frame delimiter) are appended to be the packet header by LL10GEMAC IP. At the end of packet, the zero padding (when the packet size is very small), FCS (Frame check sequence), and IFG (Interframe gap) are appended to be the packet footer. Finally, the packet is encoded by 64B/66B Encoder and scrambled before transmitting to the PMA.
■On the other hand, the received packet from the PMA is descrambled and decoded by LL10GEMAC IP. After that, FCS of the packet is verified and removed with the preamble and SFD. Only Ethernet data is forwarded to AXI4 stream interface (AXI4-ST I/F). If the FCS is not correct, the IP asserts the error signal to AXI4-ST I/F.
■When the user sends one packet to LL10GEMAC IP, the data of each packet must be always ready until end of packet. Data valid must be always asserted to ‘1’ during the packet transmission. However, ready signal from LL10GEMAC IP can be de-asserted to ‘0’ to pause data transmission for transmitting the header of 64B/66B to Sync.Gearbox module within PMA which must be sent for 2 clock cycles every 64 clock cycles.There is no transmit buffer inside LL10GEMAC IP to minimize latency time.
■In the same way, the user must be always ready to receive the packet from LL10GEMACIP because there is no received buffer inside LL10GEMAC IP. The data valid of the received packet is de-asserted to ‘0’ for 2 clock cycles every 64 clock cycles to pause data transmission when receiving the header of 64B/66B.
●Features
■10 Gbps Ethernet MAC and PCS
■Directly connecting with 32-bit PMA by Xilinx IP wizard, using Synchronous Gearbox for low latency
■Low latency solution: 16 ns for Tx interface and 9.6 ns for Rx interface
■Minimum Tx packet size: 5 bytes
■Small resource utilization
■AXI4-stream interface with the user logic
■FCS (CRC-32) inserting and checking
■64B/66B Encoding and Decoding following IEEE802.3ae specification
■Supporting 10GBASE-R standard
■Appending zero padding for Tx interface, but not removing zero padding for Rx interface
■Individual clock domain for transmit and receive interface at 312.5 MHz
■Reference design available on Xilinx development board (ZCU102)
■Customized service for following features.
▲Connection with Xilinx PMA IP in Asynchronous Gearbox for easily packet handling
▲Connection with Xilinx transceiver instead of Xilinx PMA IP for reducing the latency time
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LL10GEMAC 、 XCKU040FFVA1156-2E 、 XCZU7EV-FFVC1156-2E 、 XCVU9P-FLGA2104-2L 、 LL10GEMAC IP |
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[ High Frequency Trading ][ HFT ][ Data center ][ Real-time control system ][ Industrial ][ Automotive ][ Ethernet MAC ][ PCS ][ low latency networking ] |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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May 21, 2020 |
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Rev1.0 |
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829 KB |
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