NVMe-IP reference design manual
■NVM Express (NVMe) defines the interface for the host controller to access solid state drives (SSD) by PCI Express. NVM Express optimizes the process to issue command and completion by using only 2 register writes for command issue/completion cycle. Also, NVMe can support parallel operation by supporting up to 64K commands within single queue. So, performance for both sequential and random access is improved.
■In PCIe SSD market, user can find two standards, i.e. AHCI and NVMe. AHCI is the older standard to provide the interface for SATA hard disk drives while NVMe is optimized for non volatile memory like SSD.
■Generally, user needs to install NVMe driver to access NVMe SSD as shown in Figure 1. Physical connector of NVMe SSD is PCIe type such as M.2 connector. NVMe-IP implements NVMe driver and the task running on CPU by pure-hardware logic. So, CPU is not required to access NVMe SSD when using NVMe-IP in FPGA board.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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16-Dec-16 |
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Rev 1.1 |
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293 KB |
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