UDP25G-IP reference design
■ Comparing to TCP protocol, UDP protocol provides a procedure to send data with a minimum of protocol mechanism. There is no handshake and no data recovery process for the sender to confirm that the receiver accepts all data correctly. Similar to TCP protocol, UDP protocol provides checksum for data integrity and port numbers for addressing different functions at the source and the destination in the networks.
■ UDP25G-IP implements Transport and Internet layer of UDP/IP Protocol for building Ethernet packet from the user data (UDP payload data) to EMAC. UDP25G-IP splits the user data to a packet size and then inserts UDP/IP header. On the other hand, the received Ethernet packet from EMAC is extracted by UDP25G-IP. The header of the packet is verified and UDP payload data is forwarded to the user logic when the packet is valid. Otherwise, the packet is rejected.
■ The lower layer protocols are implemented by EMAC-IP and PCS/PMA-IP. PCS/PMA-IP is provided by Xilinx FPGA while EMAC-IP can be implemented by DG10G25GEMAC-IP or Xilinx 10/25G Ethernet Subsystem.
■ The reference design provides the evaluation system which includes simple user logic to transfer data by using UDP25G-IP. In the reference design, the target device for transferring UDP payload data with UDP25G-IP is Test PC or another UDP25G-IP on FPGA board. When running with PC, the test application for transferring UDP payload data via Ethernet connection, udpdatatest, must run.
■ To allow the user controlling the test parameters and the operation of UDP25G-IP demo via JTAG UART, the CPU system is included. It is easy for the user to set the test parameters and monitor the current status on the console. The firmware on CPU is built by using bare-metal OS. More details of the demo are described as follows.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2-Jun-21 |
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Rev1.0 |
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1.1 MB |
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