FPGA setup for TOE/UDP25G-IP with CPU Demo
■ This document describes how to setup FPGA board and prepare the test environment for running TOE25G-IP/UDP25G-IP demo. The user can setup two test environments for transfer ring TCP/UDP data via 25Gb Ethernet connection by using TOE25G-IP/UDP25G-IP , as shown in Figure 1-1.
■ Firstly, it uses one FPGA board and Test PC with 25Gb Ethernet card for transferring the data. TestPC runs test application i.e., tcpdatatest (half-duplex test for TOE25G-IP) tcp_client_ txrx_40G (full duplex test for TOE25G-IP), or udpdatatest (application test for UDP25G-IP). Also, Serial console/JTAG Terminal is run on Test PC to be user interface console .
■ Secondly, it uses two FPGA boards which may be different board . Both boards run TOE25G-IP/UDP25G-IP demo with assigning the different initialization mode (Client, Server or Fixed-MAC) for transferring data.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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7-Jun-21 |
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Rev2.0 |
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2.9 MB |
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