TOE25G-IP Core
■TCP/IP stack implementation
■Support IPv4 protocol
■Support one session per one TOE25G IP (Multisession can be implemented by using multiple TOE25G IPs)
■Support both Server and Client mode (Passive/Active open and close)
■Support Jumbo frame
■Transmitted packet size aligned to 128-bit, transmitted data bus size
■Total receive data size aligned to 128-bit, received data bus size
■Transmit/Receive buffer size, adjustable for resource and perform a nee balancing
■Simple data in terface by standard FIFO interface at 128-bit data bus
■Simple controI interface by single-port RAM in terface
■64-bit AvaIon stream to interface with 10G/25G Ethernet MAC
■At least 195.3125 MHz (25GbE)/156.25 MHz (10GbE) user clock frequency
■Support 10G/25GbE by using 10G/25G Ethernet MAC and PCS
■Reference design available on Stratix 10 GX (H-Tile) and Stratix 10 MX board
■Not support data fragmentation feature
■Customized service for following features
▲Unaligned 128-bit dab transferring
▲Buffer size extension by using Windows Scaling feature
▲Network parameter assignment by other methods
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 4, 2021 |
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Rev1.1 |
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790 KB |
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