UDP10GRx IP reference design
●When FPGA is applied for implementing UDP/IP data processor, the general solution is designed by using CPU system running UDP/IP stack as shown in the left side of Figure 1-1.Link layer and physical layer are implemented by using 10/25G Ethernet Subsystem which is Xilinx IP core. This solution is flexible for many applications because the user designs the software,run on CPU.The disadvantage of this solution is the latency time for processing the packet which is much from the overhead time for the hardware interfacing with the software.
●Design Gateway provides the full hardwired logic system for processing UDP/IP packet as shown in the right side of Figure 1-1. UDP10GRx-IP is the hardware to process UDP/IP packet which is received from Low-latency Ethernet MAC IP (LL10GEMACIP). Both IPs are provided by Design Gateway. The lowest layer in the hardware is PMA IP which is free IP, provided by Xilinx. The UDP data is extracted from the packet and then forwarded to the user logic by using simple interface. Up to four sessions are supported by UDP10GRx-IP at the same time.
|
|
|
|
Application note & Design Guide |
|
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
|
23-Jun-20 |
|
|
Rev1.0 |
|
|
|
|
|
944 KB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
