TOE1G-IP Multisession Reference design manual
■Multi-session demo is designed by implementing eight TOE1G-IPs to support data transfer by using eight sessions at the same time. Comparing to half duplex demo, 8-to-1 EMAC multiplexer is additional designed to share transmit channel of one EMAC-IP to all TOE1G-IPs. Asynchronous buffer between receive channel of EMAC-IP and TOE1G-IP is designed to convert data in regional clock domain to be global clock domain for easily routing to eight TOE1G-IPs. The buffer size of each TOE1G-IP in multisession demo is reduced from 64Kbyte size to 8Kbyte size to allow user adding more TOE1G-IP in the design without resource limitation. But reducing buffer size will reduce transfer performance.
■To run the demo, TestPC must run “tcpdatatest.exe” application which is provided by Design Gateway to send/receive data with FPGA.
|
|
|
|
|
|
|
Application note & Design Guide |
|
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
|
19-May-17 |
|
|
Rev 1.0 |
|
|
|
|
|
213 KB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
