TOE1G-IP with CPU reference design
●TCP/IP is the core protocol of the Internet Protocol Suite for networking application. TCP/IP model has four layers, i.e. Application Layer, Transport Layer, Internet Layer, and Network Access Layer. As shown in Figure 1-1, five layers are displayed for simply matching with the hardware implementation on FPGA. Network Access Layer is split into Link and Physical Layer.
●TOE1G-IP implements Transport and Internet layer of TCP/IP Protocol for building Ethernet packet from the user data which is TCP data to EMAC. TOE1G-IP splits TCP data from the user to small packet and then inserts TCP/IP header. On the other hand, the received Ethernet packet from EMAC is extracted by TOE1G-IP. The header of the packet is verified and TCP data is forwarded to the user logic when the packet is valid. Otherwise, the packet is rejected.
●The lower layer protocols are implemented by EMAC-IP and external PHYIC.
●The reference design provides the evaluation system which includes simple user logic to transfer data by using TOE1G-IP. TOE1G-IP is designed to transfer data with PC or another TOE1G-IP on another FPGA board. To run with PC, the test application is called on PC to send and verify TCP data via Ethernet connection at high-speed rate. Two test applications are specially designed, i.e. “tcpdatatest” for half-duplex test (send or receive data test) and “tcp_client_txrx_40G” for full-duplex test (send and receive data at the same time).
●To allow the user controlling the test parameters and the operation of TOE1G-IP demo via UART, the CPU system is included. It is easy for the user to set the test parameters and monitor the current status on UART console.The firmware on CPU is built by using bare-metal OS. More details of the demo are described as follows.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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31-Jul-20 |
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Rev1.1 |
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835 KB |
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