TOE1G-IP with CPU reference design
●TCP/IP is the core protocol of the Internet Protocol Suite for networking application. TCP/IP model has four layers, i.e. Application Layer, Transport Layer, Internet Layer, and Network Access Layer. As shown in Figure 1-1, five layers are displayed for simply matching with the hardware implementation on FPGA. Network Access Layer is split into Link layer and Physical layer.
●TOE1G-IP implements Transport and Internet layer of TCP/IP Protocol. Building Ethernet packet from the user data which is TCP data to EMAC, TOE1G-IP splits TCP data from the user to small packet and then inserts TCP/IP header. On the other hand, the received Ethernet packet from EMAC is extracted by TOE1G-IP. The header is applied to verify the packet and TCP data is forwarded to the user logic. The packet is rejected when TCP/IP header in the packet is invalid.The lower layer protocols are implemented by EMAC-IP from Intel FPGA and external PHY chip.
●The reference design provides the evaluation system which includes simple user logic to send and receive data by using TOE1G-IP. TOE1G-IP is designed to transfer data with PC or another TOE1G-IP running on another FPGA board. To run with PC, the test application is called on PC to send and verify TCP data from Ethernet connection at high speed rate. Two test applications are specially designed for running the demo, i.e. “tcpdatatest” for half-duplex test (send or receive data test) and “tcp_client_txrx_40G” for full-duplex test(send and receive data at the same time).
●To allow the user controlling the test parameters and the operation of TOE1G-IP demo through JTAG UART, the CPU system is included. It is easy for the user to set and monitor the test parameters and the system status on the console through JTAG UART. The firmware on CPU is built by using bare-metal OS. More details of the demo are described as follows.
●TOE1G-IP needs to connect to Triple-Speed Ethernet MAC and Ethernet PHY which implement lower-layer protocol.The user interfaces of TOE1G-IP are connected to User Reg for both control and data interface. For data interface, User Reg includes PattGen logic to generate test pattern for sending data and Verify Patt logic to generate test pattern for verifying received data.Test pattern generated in UserReg is 32-bit incremental pattern.
●For control interface, UserReg includes register to store parameters from user such as transfer length, transfer direction, and transfer mode which are set through JTAG UART. CPU converts the user parameters to be value for setting to hardware register through Avalon bus. Due to the fact that CPU system and TOE1G-IP run in different clock domain, AsyncAvlReg module is applied to be asynchronous circuit to support clock-crossing function and then convert Avalon bus signal which is standard bus in CPU system to be register interface.CPU in the demo is NiosII and runs on bare-metal OS. CPU system includes JTAG UART hardware for user interface and timer to measure transfer performance.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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6-Dec-19 |
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Rev1.1 |
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926 KB |
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