UDP25G-IP Core Product Specification
■ UDP/IP stack implementation
■ Support IPv4 protocol
■ Support Full-duplex transfer, Tx port and Rx port independently assigned
■ Support more sessions by using multiple UDP25G IPs
■ Support Jumbo frame
■ Transmit packet size aligned to 128-bit, bus size of transmitted data
■ Total receive data size aligned to 128-bit, bus size of received data
■ Several Transmit/Receive buffer sizes
■ Simple data interface by 128-bit FIFO interface
■ Simple control interface by single-port RAM interface
■ 64-bit AXI4 stream to interface for 10G/25G Ethernet MAC
■ User clock frequency must be more than or equal to 195.3125 MHz for 25Gb Ethernet/156.25 MHz for 10Gb Ethernet
■ Support 10G/25GbE by using 10G/25G Ethernet MAC and PCS
■ Reference design available on KCU116 board/FB2CGHH@KU15P card
■ Support IP fragmentation
■ Customized service for following features
▲ Multicast IP
▲ Unaligned 128-bit data transferring
▲ Network parameter assignment by other methods
● General Description:
■ UDP25G IP core implements UDP/IP stack by hardware logic and connects with 10/25 Gb EMAC IP and PCS/PMA (BASE-R) module as the lower layer hardware. User interface of UDP25G IP consists of two interfaces, i.e., Register interface for control signals and FIFO interface for data signals.
■ Register interface has 5-bit address for accessing up to 32 registers, consisting of network parameters, command register, and system parameters. The IP uses two sessions for transmitting data and receiving data at the same time, one session for one direction. The network parameters assigned in both sessions are similar, except the port number on target device. The parameters of UDP25G IP and the target device are assigned by the user before starting IP initialization. After that, the network parameters cannot be changed. The reset process is necessary to change some network parameters. The initialization process has three modes to get MAC address of the target device. After finishing the initialization process, the IP is ready for transferring data with the target device.
■ To send the data, the user sets total transfer size and packet size to the IP and then transfers the data via TxFIFO interface which is 128-bit data size. When the data is received from the target, the user reads the received data from the IP via RxFIFO interface.
■ The buffer size inside the IP can be assigned by the user. In Tx path, two buffers can be adjusted, Tx data buffer and Tx packet buffer. In Rx path, one buffer is available, named Rx data buffer. The buffer size must be much enough to store at least two data packets. If user logic does not pause data transferring with UDP25G IP, Tx data buffer and Rx data buffer will be always ready status. Therefore, the buffer size can be set as minimum value. Bigger buffer size is applied to store the data when the user logic is sometimes not ready for transferring data with UDP25G IP.
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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June 2, 2021 |
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Rev1.0 |
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718 KB |
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