TOE100G-IP Core
■TCP/IP stack implementation
■Support IPv4 protocol
■Support one session by one TOE100G IP (Multisession can be implemented by using multiple TOE100G IPs)
■Support both Server and Client mode (Passive/Active open and close)
■Support Jumbo frame Packet size for transmitting aligned to 512-bit. transmitted data bus size
■Total received data size aligned to 512-bit, received data bus size
■Simple data in terface by standard FIFO interface at 512-bit data bus
■Simple controI interface by single port RAM interface
■512-bit AXI4 stream interface with 100G Ethernet MAC
■At least 240 MHz user clock frequency
■Reference design available on KCU116 board/Alveo U250 card4zB2CGHH@KU15P card ■Not support data fragmentation feature
■Customized service for following features
▲Unaligned 512・bit data transferring
▲Buffer size extension by using Windows Scaling feature
▲Network parameter assignment by other methods
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April.27.2021 |
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Rev1.1 |
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947 KB |
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