TOE25G-IP Core Product Specification
■TOE25G IP core implements TCP/IP stack by hardware logic and connects with 10/25 Gb EMAC IP and PCS/PMA (BASE-R) module as the lower layer hardware. User interface of TOE25G IP consists of two interfaces, i.e. Register interface for control signals and FIFO interface for data signals.
■Register interface has 5-bit address for accessing up to 32 registers, consisting of network parameters, command register and system parameters. The IP supports only one session, so the network parameters set by the user are fixed for assigning to TOE25G IP and the target device. After that, start IP initialization by de-asserting reset signal. Also, the reset process is necessary when some network parameters must be changed. The initialization process has three modes to get MAC address of the target device. After finishing the initialization process, the IP is ready for transferring data with the target device.
■Following TCP/IP standard, the connection must be created by opening the port as the first step. The IP supports for both active open (the port opened by the IP) or passive open (the port opened by the target device). After that, data can be transferred from both sides. To send the data, the user sets total transfer size and packet size to the IP and then transfers the data via TxFIFO interface which is 128-bit data size. When the data is received from the target, the user reads the received data from the IP via RxFIFO interface. After finishing data transferring, the connection can be destroyed by using active close (the port closed by the IP) or passive close (the port closed by the target).
■To meet the user system requirement which may be sensitive on the memory resource or the performance, the buffer size inside the IP can be assigned by the user. In Tx path, two buffers can be adjusted, i.e. Tx data buffer and Tx packet buffer. In Rx path, one buffer is available, named Rx data buffer. Using the bigger buffer size may increase the transfer performance in each direction. More details of the hardware inside the IP are described in the next topic.
●Features
■TCP/IP stack implementation
■Support IPv4 protocol
■Support one session per one TOE25G IP (Multisession can be implemented by using multiple TOE25G IPs)
■Support both Server and Client mode (Passive/Active open and close)
■Support Jumbo frame
■Transmit packet size aligned to 128-bit, bus size of transmitted data
■Total receive data size aligned to 128-bit, bus size of received data
■Transmit/Receive buffer size, adjustable for resource and performance balancing
■Simple data interface by 128-bit FIFO interface
■Simple control interface by 32-bit Register interface
■64-bit AXI4 stream to interface for 10G/25G Ethernet MAC
■User clock frequency must be more than or equal to 195.3125 MHz for 25Gb Ethernet/156.25 MHz for 10Gb Ethernet
■Support 10G/25GbE by using 10G/25G Ethernet MAC and PCS
■Reference design available on VCU118/KCU116 board
■Not support data fragmentation feature
■Customized service for following features
▲Unaligned 128-bit data transferring
▲Buffer size extension by using Windows Scaling feature
▲Network parameter assignment by other methods
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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September 15, 2020 |
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Rev1.2 |
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785 KB |
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