TOE10GLL IP Core Product Specification
■TOE10GLL IP implements TCP/IP stack by hardwire logic for transfering 10Gb Ethernet packet with ultra-low latency. User interface of TOE10G IP consists of three interfaces, i.e., Network parameter interface for control signals, Transmit data interface and Receive data interface.
■To create TCP connection, the user needs to setup the network parameters for communicating with another device via 10Gb Ethernet. TOE10GLL IP receives the parameters from Control I/F such as MAC address, IP address and Port number. Besides, the initialization mode and command are the signals in Control I/F which is set by the user. After reset is de-asserts, Control block starts IP initialization to get MAC address of the target device, following the initialization mode by using the network parameters from user. After that, the IP is ready for transferring data with the target device.
■Following TCP/IP standard, the connection must be created by opening the port as the first step. The user can select to open the port as active mode (Client) or passive mode (Server). Similarly, the connection can be terminated as active mode or passive mode. The data can be transferred when the connection is active. The user can send the data with setting packet size via Transmit data interface of TOE10GLL IP. On the contrary, when TOE10GLL IP receives the packet, the data in the packet is decoded and returned to the user via Receive data interface.
■Tx data buffer size can be set as TOE10GLLIPparametersfor balancing the memory resource utilization against transfer performance in the system. More details of the hardware inside the IP are described in the next topic.
●Features
■TCP/IP stack implementation
■Support IPv4 protocol without IP fragmentation
■Ultra-low latency data transmission
▲6.2 ns latency time for transmitting data
▲46.5 ns latency time for receiving data
■Support one session per one TOE10GLL IP(using multiple TOE10GLL IPs for multi-sessions)
■Support Server and Client mode
■Supported payload data size
▲1-1460 byte per packet for transmitted data(normal frame size, not jumbo frame)
▲1-16000 byte per packet for received data
■Transmit data buffer size: 4.6kByte –73.7kByte
■User interface: 32-bit data streaming interface
■EMAC interface: 32-bit AXI4-stream interface for connecting with DG LL10GEMAC IP or Xilinx 10G/25Gb Ethernet Subsystem
■Individual clock domain for transmit and receive interface at 322.265625 MHz(synchronous gearbox)or 312.5 MHz (asynchronous gearbox)
■Reference design available on ZCU102 and ZCU106 board
■Customized service for following features
▲Jumbo frame support
▲Buffer size extension by Window scaling feature
▲Customized user interface
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XCKU040FFVA1156-2E 、 XCZU9EG-FFVB1156-2-I 、 XCVU9P-FLGA2104-2L |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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November 3, 2020 |
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Rev1.0 |
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1.7 MB |
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