UDP40G-IP reference design
■Comparing to TCP protocol, UDP protocol provides a procedure to send data with a minimum of protocol mechanism, but the data cannot guarantee to be accepted by the destination because of no handshaking dialogues providing in UDP mechanism.Similar to TCP protocol, UDP protocol provides checksums for data integrity and port numbers for addressing different functions at the source and the destination in the communication networks.
■UDP40G-IP implements Transport and Internet layer of UDP/IP model. To send data, UDP40G-IPpreparesUDP data from user logic,adds UDP/IP header to generate Ethernet packet,and sends to EMAC. To receive data, UDP40G-IP extracts UDP data and header from Ethernet packet. When UDP/IP header in the packet is valid, UDP data is stored to the buffer for user logic reading.
■The lower layer protocols are implemented by 40GbEthernet MAC IP and PHY IP.In the reference design, both IPs are the IP core from Xilinx.
■This reference design provides evaluation system which includes simple user logic to send and receive data by using UDP40G-IP. For user interface, CPU system is designed to interface with user through Serial port. The firmware is designed as bare-metal OS (no operating system).The test application software (“udpdatatest.exe”), run on PC,is also designed for sending and receiving UDP/IP packet with UDP40G-IP. The reference design is available on Xilinx development board to show ultra-speed data transferring.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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22-Oct-19 |
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Rev 1.0 |
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1 MB |
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