UDP40G-IP Core Product Specification
■UDP40GIP core implements UDP/IP stack by hardware logic and connects EMAC and PCS/PMA (BASE-R) module through Adapter logic as the lower layer hardware. User interface of UDP40G IP consists of two interfaces, i.e. Register interface for control signals and FIFO interface for data signals.
■Register interface has 4-bit address for accessing up to 16 registers, consisting of network parameters, command register and system parameters. The IP uses two sessions for transferring data in bi-directional, one session for one direction. All network parameters of both sessions must be similar, except the port number on the target device. The network parameters are assigned by the user to be fixed value for both UDP40GIP and the target device before starting IP initialization. The reset process is necessary when some network parameters must be changed. The initialization process has two modes to get MAC address of the target device. After finishing the initialization process, the IP is ready for transferring data with the target device.
■To send the data, the user sets total transfer size and packet size to the IP and then transfers the data via TxFIFO interface which is 256-bitdata size. When the data is received from the target, the user reads the received data from the IP via RxFIFO interface.
■To meet the user system requirement which may be sensitive on the memory resource or the performance, the buffer size inside the IP can be assigned by the user. Tx data buffer and Rx data buffer can be adjusted for Tx path and Rx path respectively. Buffer size in the IP is applied to be the data buffer between user logic and EMAC. Using bigger buffer size, the user logic can switch to run other tasks for longer time before switching back to transfer the data with UDP40G IP.
●Features
■UDP/IP stack implementation
■Support IPv4 protocol
■Full-duplex transferring by using two port numbers for each transfer direction
■Support more sessions by using multiple UDP40GIPs
■Support Jumbo frame
■Packet size for transmit must be aligned to 256-bit because Transmit data bus size is 256-bit
■Received data bus size is 256-bit, so total receive size must be aligned to 256-bit
■Transmit/Receive buffer size, adjustable for optimizing resource and performance
■Simple data interface by standard FIFO interface
■Simple control interface by single port RAM interface
■256-bit FIFO interface with Ethernet MAC
■At least 200 MHz is recommended for clock input to UDP40G IP
■Reference design available on ZCU102, ZCU106and KCU105 evaluation board
■Support IP fragmentation feature
■Customized service for following features
▲Multicast IP
▲Unaligned 256-bit data transferring
▲Network parameter assignment by other methods
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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October 2, 2020 |
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Rev1.1 |
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712 KB |
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