TOE40G-IP Core Product Specification
■TOE40G IP core implements TCP/IP stack by hardwire logic and connects with EMAC and PCS/PMA (BASE-R) module through Adapter logic as the lower layer hardware. User interface of TOE40G IP consists of two interfaces, i.e. Register interface for control signals and FIFO interface for data signals.
■Register interface has 4-bit address for accessing up to 16 registers, consisting of network parameters, command register and system parameters. The IP supports only one session, so the network parameters set by the user are fixed for assigning to TOE40G IP and the target device. After that, start IP initialization by de-asserting reset signal. Also, the reset process is necessary when some network parameters must be changed. The initialization process has two modes to get MAC address of the target device. After finishing the initialization process, the IP is ready for transferring data with the target device.
■Following TCP/IP standard, the connection must be created by opening the port as the first step. The IP supports for both active open (the port opened by the IP) or passive open (the port opened by the target device). After that, data can be transferred from both sides. To send the data, the user sets total transfer size and packet size to the IP and then transfers the data via TxFIFO interface which is 256-bit data size. When the data is received from the target, the user reads the received data from the IP via RxFIFO interface. After finishing data transferring, the connection can be destroyed by using active close (the port closed by the IP) or passive close (the port closed by the target).
■To meet the user system requirement which may be sensitive on the memory resource or the performance, the buffer size inside the IP can be assigned by the user. Tx data buffer and Rx data buffer can be adjusted for Tx path and Rx path respectively. Using the bigger buffer size may increase the transfer performance in each direction. More details of the hardware inside the IP are described in the next topic.
●Features
■TCP/IP stack implementation
■Support IPv4 protocol
■Support one session by one TOE40G IP(Multisession could be implemented by using multiple TOE40G IPs)
■Support both Server and Client mode (Passive/Active open and close)
■Support Jumbo frame
■Packet size for transmit must be aligned to 256-bit because Transmit data bus size is 256-bit
■Received data bus size is 256-bit, so total receive size must be aligned to 256-bit
■Transmit/Receive buffer size, adjustable for optimizing resource and performance
■Simple data interface by standard FIFO interface
■Simple control interface by single port RAM interface
■256-bit FIFO interface with Ethernet MAC
■At least 200 MHz is recommended for clock input to TOE40G IP
■Reference design available on ZCU102, ZCU106 and KCU105 evaluation board
■Not support data fragmentation feature
■Customized service for following features
▲Unaligned 256-bit data transferring
▲Buffer size extension by using Windows Scaling feature
▲Network parameter assignment by other methods
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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October 2, 2020 |
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Rev1.2 |
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760 KB |
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