NVMe IP with PCIe Gen3 Soft IP reference design manual
■NVM Express (NVMe) defines the interface for the host controller to access solid state drive (SSD) by PCI Express. NVM Express optimizes the process to issue command and completion by using only two registers (Command issue and Command completion). Otherwise, NVMe supports parallel operation by supporting up to 64K commands within single queue. 64K command entries improve transfer performance for both sequential and random access.
■In PCIe SSD market, two standards are used, i.e.AHCI and NVMe. AHCI is the older standard to provide the interface for SATA hard disk drive while NVMe is optimized for non volatile memory (SSD).
■Conventionally, the NVMe host is implemented by using PC or CPU operating with PCIe controller for transferring data with NVMe SSD.NVMe protocol is designed as the driver and communicates with the PCIe controller hardware which is CPU peripherals connected throughvery high-speed bus. External memory is applied for transferring data between PCIe controller and SSD.
■The new solution is purposed by using DG NVMe IP, as shown in Figure 1-1. Without CPU and external main memory usage, the NVMe host can be implemented within FPGA by using NVMe IP and Integrated Block for PCIe (PCIe hard IP). This solution uses less FPGA resource and achieves ultra-speed write and read performance.The limitation of this solution is the availability of PCIe hard IP which is included only some FPGA models. Otherwise, the maximum number of SSDs are limited by the number of PCIe hard IPs
■This document presentsthelatest solution from Design Gateway. The NVMe host IP can be implemented in the low-cost FPGAor no PCIe hard IP FPGA by using DG NVMeG3 IP. The new IP implements the lower layer of PCIe protocol, i.e. Data Link Layer and some parts of Physical Layer by using the logic. This feature is known asPCIe soft IP.By integratingPCIe Soft IP and NVMe IP, NVMe G3 IP connecting with Xilinx PCIe PHY IP is the recent solution for implementing NVMe host in FPGA.
■User interface and performance of DG NVMe IP andDG NVMeG3 IP are similar.The user can use the same user logic for running NVMe IP or NVMeG3 IP.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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30-Aug-19 |
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Rev 1.0 |
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404 KB |
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