Lattice Sentry Embedded Security Block Mux IP Core for MachXO3D -Lattice Propel Builder User Guide
■This document describe show to select between the two available logical interfaces of the MachXO3D™ Embedded Security Block (ESB). The ESB has two logical interfaces for sending and receiving data: a WISHBONE register interface and a High Speed Data Port (HSP) FIFO-style interface. These two logical interfaces share one physical data interface with the ESB (one shared 32-bit input port and one shared 32-bit output data port). The WISHBONE interface of the ESB is converted to an APB (Advance Peripheral Bus ) interface for RISC-V CPU access.
■The design is implemented in Verilog HDL. It can be configured and generated using Lattice Propel™Builder. It can be targeted to MachXO3D FPGA devices and implemented using the Lattice Diamond® software Place and Route tool integrated with the Synplify Pro® synthesis tool.
●Features
■The key features of the ESB Mux IP include:
▲Soft wrapper around the ESB to provide separate APB and high-speed port interfaces to user logic
▲Support for AMBA 3 APB Protocol v1.0
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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May 2020 |
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Revision 1.0 |
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FPGA-IPUG-02107-1.0 |
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777 KB |
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