MachXO2 sysCLOCK PLL Design and Usage Guide Technical Note
■MachXO2™ devices support a variety of I/O interfaces such as display interfaces (7:1 LVDS) and memory interfaces (LPDDR, DDR, DDR2). In order to support applications which use these interfaces, the MachXO2 device architecture has been designed to include advanced clocking features that are typically found in higher density FPGAs. These features provide designers the ability to synthesize clocks, minimize clock skew, improve performance and manage power consumption.
■This technical note describes the clock resources available in the MachXO2 devices. Details are provided for primary clocks, edge clocks, clock dividers, sysCLOCK™ PLLs, DCC elements, the secondary high fan-out nets, and the internal oscillator available in the MachXO2 device.
|
MachXO2 、 MachXO2-1200 、 MachXO2-256 、 MachXO2-640 、 MachXO2-640U 、 MachXO2-1200U 、 MachXO2-2000 、 MachXO2-2000U 、 MachXO2-4000 、 MachXO2-7000 |
|
|
|
|
|
Application note & Design Guide |
|
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
|
March 2020 |
|
|
Revision 2.8 |
|
|
FPGA-TN-02157-2.8 |
|
|
1.7 MB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
