E600Saa Series AF016GEC5X-2001A2/AF032GEC5X-2001A2/AF064GEC5X-2001A2/AF128GEC5X-2001A2 Automotive-Gradee.MMC Data Sheet
The automotive-grade ATP e.MMC (Embedded MultiMediaCard) solution is designed to meet high-performance data transfer, code, data storage, infotainment, and other automotiveapplication requirements. Compliant with the latest JEDEC e.MMC v5.1 specification, the ATP e.MMC is an embedded storage solution consisting of an MMC interface, flash memory and controller integrated in the same IC package andoffered in an industry standard ball grid array (BGA) package. The integrated package simplifies the application interface design, makingthe ATP e.MMC suitable for automotive and industrial applications requiring rugged endurance, reliability and durability in challenging operating environments.
Enhanced v5.1 features include Command Queuing, High Speed 400 (HS400) DDR Mode for a bandwidth of up to 400 MB/s, andfield firmware update (FFU). The ATP e.MMC 5.1 is backward compatible with other versions, supporting v4.51 features such as power-off notifications, packed commands, cache, boot or replay protected memory block (RPMB) partitions, high priority interrupt (HPI), and hardware (HW) reset.
Constructed using 3D MLC NAND flash memory, the ATP e.MMC achieves higher densities with upto 128 GB of memory for use in mass storage applications. The MMC interface allows easy integration with any microprocessor with MMC host. Any revision to or amendment of the NAND is invisible to the host as the embedded MMC controller insulates NAND technology from the host, leading to faster product development as well as faster time to market.
To ensure the highest levels of performance, utmost reliability, better endurance, and product longevity, the ATP e.MMCemploys proprietary solutions such as Advanced Global Wear Leveling along with SSD-level low-density parity check error correction code (LDPC ECC) technology, Dynamic Data Refresh, AutoRefresh, SRAM soft error detector technology for monitoring error bit levels during device operation to ensure data integrity, and the Early Retirement technology to prevent data loss from weak blocks.
The ATP e.MMC also incorporates the S.M.A.R.T. (Self-Monitoring, Analysis, and Reporting Technology) function into Health Report to monitor various parameters of endurance and reliability, indicating activity that is out of the normal range. This information helps predict storage failure for preventive action.
Features Summary
• AEC-Q100 Grade 2 Compliant
• 153-ball FBGA (RoHS compliant, Green Package), Ball pitch is 0.5mm
• VCC: 2.70V~3.60V
• VCCQ(dual voltage): 1.70V~1.95V and 2.70V~3.60V
• Data Bus Width: 1-bit, 4-bit, 8-bit
• SDR52/DDR52 MHz Mode; HS200/HS400 Mode
• Temperature Ranges (ambient)
■ Operating Temperature: -40°C to +105°C
■ Storage Temperature: -40°C to +105°C
• Gold Wire Bonding
• Dynamic Data RefreshTechnology
• AutoRefresh Technology
• SRAM Soft Error Detector Technology
• Sudden Power-Off Recovery (SPOR)
• Early Retirement Technology
• S.M.A.R.T. (Self-Monitoring, Analysis, and Reporting Technology)
• LDPC-ECC and Block Management
• JEDEC/MMC Standard Ver. 5.1 Compliant (JEDEC Standard No. JESD84-B51)
■ Backward Compatible with Previous e.MMC versions
■ Enhanced Strobe in HS400 Mode
■ Field Firmware Update (FFU)
■ Boot Operation (High-Speed Boot)
■ RPMB (Replay Protected Memory Block)
■ Device Health Report
■ Production State Awareness(PSA)
■ Sleep/Power-Off Notification
■ Packed Commands
■ Reliable Write
■ Secure Write Protection
■ Discard, Sanitize, Secure Erase, Secure Trim
■ Cache,Cache Barrier, Cache Flushing Report
■ Real Time Clock
■ Context ID
■ Data TAG
■ Hardware Reset
■ HPI (High Priority Interrupt)
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E600Saa 、 AF016GEC5X-2001A2 、 AF032GEC5X-2001A2 、 AF064GEC5X-2001A2 、 AF128GEC5X-2001A2 |
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Datasheet |
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Please see the document for details |
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FBGA;BGA |
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English Chinese Chinese and English Japanese |
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Revision 1.1 |
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3.4 MB |
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