Brite Semiconductor Introduces Zero-Latency and True-Adaptive technologies for High-speed DDR PHY
Shanghai, China—Jul.7, 2022—Brite Semiconductor (“Brite”), a leading custom ASIC & IP provider, today announced the launch of Zero-Latency and True-Adaptive technologies for high-speed DDR PHYs. These technologies have already begun to be deployed on 22/28nm DDR4/LPDDR4, 4x high-performance PHY IPs, which will bring customers a whole new experience with higher efficiency and stability.
Unlike other DDR PHY vendors who use FIFO for cross-clock domain conversion, Zero-Latency technology adopts two optional and unique sampling methods for data transfer on the read data path, which minimizes latency and saves the silicon area.
True-Adaptive technology always tracks the voltage temperature in the chip, the variation in the round-trip delay between the chip and the memory, and the skew of the read DQ/DQS, choosing an appropriate time to compensate. With this technology, users only need to train once after power is on, and then the PHY will track and compensate automatically, which can completely eliminate the bandwidth loss caused by retraining.
Yadong Liu, VP of Engineering at Brite Semiconductor said, "Brite Semiconductor has been deeply engaged in DDR PHY technology for many years, and has been committed to architecture innovation. The number of customers who are using PHY IP based on these technologies is increasing. Brite Semiconductor will pursue to better meet customer needs and bring higher value to customers."
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