Brite Semiconductor Releases Gen2 DDR LP PHY IP Based on 40LL Process, Supporting RD DQS Falling Edge Training Mode
Brite Semiconductor (“Brite”), a world-leading ASIC design service and DDR controller/PHY IP provider headquartered in Shanghai, China, today announced the availability of the second generation of DDR Low Power (LP) PHY IP based on 40LL process, with a 20% reduction in area, 37% in power consumption and 50% in physical implementation cycle, compared to the first generation.
The second generation of DDR Low Power PHY adopts dual row IO structure and many other logical and physical optimization means, which results in reducing the area of delay chains by 20%, decreasing the delay variations of DQ and DQS, and eliminating the balance of wire loadings and buffers among DQ and DQS. These directly lead to the increase of the utilization of silicon area and the DDR speed, and the decrease of the power consumption.
The second generation of DDR LP PHY IP has the following characteristics:
1. Based on 40LL Process
2. Achieve 1333Mbps in DDR3/3L/3U/LPDDR3 and 1066Mbps in DDR2/LPDDR2
3. Support PHY evaluation training or software training mode
4. Support RD DQS falling edge training mode
5. Support AHB/APB3.0 registers interface
“Brite Semiconductor has 10-year successful experience of ASIC design service and the rich accumulation in complete DDR IP solution. There are more than 20 projects which adopted Brite’s DDR IP technology and taped out successfully on 28HKMG, 40LL, 55LL and 130nm processes, covering the applications of DTV, AP, navigation and NVDIMM,” said John Zhuang, Chief Technology Officer at Brite Semiconductor. “We will continue to carry out the structure innovation and improve the quality of service and the implementation process so as to provide more competitive solutions for our valuable customers.”
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