Brite Semiconductor Now Provides a Total Solution of xSPI Controller and PHY for the Advanced Memory and SPI Device
Shanghai, China—Aug.5, 2022—Brite Semiconductor (“Brite”), a leading custom ASIC & IP provider, today announced providing xSPI/HyperbusTM/XcellaTM memory (Flash, PSRAM, MRAM…) controller and PHY solution for custom SoC. This solution is verified using memories from memory manufacturers such as GigaDevice, APMemory, Cypress (Infineon), Micron, Macronix, etc., which can support customers to develop better products faster in different fields.
The expanded Serial Peripheral Interface (xSPI) JESD251 standard, ratified by JEDEC in July 2018, defines a high-data throughput, serial interface for memory. It provides high data throughput, and low pin count and is primarily for use in computing, automotive, Internet of Things (IoT), embedded systems, and mobile systems, between host processing and peripheral devices. The xSPI electrical interface can deliver up to 400MT/s raw data throughput. It is mainly for nonvolatile memory devices for example NOR flashes and NAND flash, and a large number of memory vendors adopt it for PSRAM (Pseudo SRAM) or MRAM (Magnetic RAM). It is extensible for a higher data rate based on either a high data rate per bit or a wider data path， achieving 800MT/s.
Brite Semiconductor now can provide a total solution of xSPI controller and PHY for the advanced memory and also legacy Octal SPI device, QSPI device, and SPI device. Brite Semiconductor adopts auto-flow-control technology to minimize the FIFO/SRAM utilization. Also, another innovative feedback-sampling technology is used to increase the data rate which doesn’t have a DS, achieving a maximum of 400MT/s in 8D mode without DS. The solution has the following features:
Support Flash, PSRAM, and MRAM using SPI protocol
Support Single/Dual/Quad/Octal SDR/DTR(DDR) SPI
Support xSPI/HyperbusTM/XcellaTM specification
Support xSPI profile1 and profile2 (HyperbusTM)
Support XIP (eXecute-In-Place) for fast boot
Support AXI burst type INCR/WRAP and Fixed (single beat)
Support AXI data width 32/64/128… bit
Support AXI strobe width 4/8/16... bit
Support AXI maximum burst length of 256
Support AXI outstanding command, configurable outstanding capability
Support maximum 4 CSn
Support 3 Bytes or 4 Bytes address
Support single-ended or differential clock
Support with/without DS, no performance degradation without DS
Three clock domains: APB, AXI, xSPI clock
xSPI clock maximum frequency 200Mhz
Full digital PHY, 1x clock, small area, over-sampling is unnecessary
Maximum data rate 400MT/s (DDR, DTR) or 200MT/s (SDR)
Support arbitrary commands through the APB register interface (READ SFDP, ERASE, etc.)
Programmable READ/WRITE command code
Support 2x dummy cycles (extensible dummy cycles)
Note: HyperbusTM is a trademark of Cypress(Infineon), and XcellaTM is a trademark of Micron.
"There is a greater demand for high throughput and low pin count for Industrial IoT, Automotive, and Edge AI applications, the emergence of xSPI memory can meet such requirement,” said Yadong Liu, VP of Engineering at Brite Semiconductor. “In addition, Brite Semiconductor expands the DDR technologies to xSPI, adopting auto-flow-control and feedback-sampling technologies to achieve low area and high data rate, then provides the total solution of xSPI memory controller for the custom SoC."
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