Brite Semiconductor Releases ONFI 4.2 IO and Physical Layer IP based on SMIC 14nm FinFET Process

PublishTime： 2023-08-31 Article Source：灿芯半导体官网

Brite Semiconductor (“Brite”), a leading provider of custom ASIC design, manufacturing and IP, on Jun.3, 2021 announced the launch of ONFI (Open NAND Flash Interface) 4.2 IO and Physical Layer IP. The IO supports SDR/NV-DDR/NV-DDR2 1.8V, NV-DDR3 1.2V, and the physical layer IP adopts full digital design with features of low power consumption and small area.

The ONFI physical layer IP can be adopted in the ONFI and is compatible with ONFI 4.2/4.1/4.0/3.2 etc. standards. Currently, the IO and physical layer IP is silicon proven on 40nm processe.

ONFI 4.2 physical layer IP has the following features:

1. Silicon proven on 40LL process

2. Achieve Max 1600Mbps on NV_DDR3 1.2V and Max 800Mbps on NV_DDR2 1.8V

3. Achieve Max 800Mbps on 40LL

4. Support ODT (On-Die Termination) and Impedance calibration

5. Compliant with the ONFI 4.2/4.1/4.0/3.2 etc. standard

6. Support DQS Gate, Write and Read training

7. Adopt All-Digital DLL design

8. Adopt APB register interface

“With more than 10 years of successful experience of custom ASIC design, manufacturing and IP development, Brite Semiconductor provides the value to our customers,” said Yadong Liu, VP of Engineering at Brite Semiconductor. “The ONFI IP is silicon proven , which can help customers quickly achieve mass production.”

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