Smiths Interconnect‘s DaVinci 112 Test Socket Shortlisted for 2024 World Electronics Achievement Awards
Smiths Interconnect is proud to announce that its DaVinci 112 test socket has been shortlisted as one of the top Test & Measurement products for the 2024 World Electronics Achievement Awards, hosted by AspenCore.
The World Electronics Achievement Awards recognize companies and individuals who have made exceptional contributions to innovation and the development of the global electronics industry. Being shortlisted for this prestigious award is a testament to Smiths Interconnect's commitment to advancing technology and delivering cutting-edge solutions.
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Smiths Interconnect announced the expansion of its DaVinci Series to incorporate DaVinci 112 - ideal for testing the most complex functionality of Application Specific Integrated Circuits (‘ASICs’). With DaVinci 112, Smiths Interconnect has achieved full coverage of the product line for high-speed test of 0.35mm pitch and above. Historically Cloud, Data centers, Artificial Intelligence, and Connected Automotive segments have all used CPUs or GPUs that were intended for other applications. As the performance, functionality and size of the chips for these end-use applications continue to increase, now companies are designing and manufacturing Application Specific Integrated Circuits intended solely for the end segment.
Addressing high-speed signaling, device complexity, and power requirements, the pin count is well over 4000 I/O’s all working in tandem to meet the specification. At the same time, testing these devices in full functionality is difficult due to noise isolation. DaVinci 112 test socket change in mechanical structure ensures the ground probe is always in contact with the socket body. This improved ground path offers a cleaner power delivery and is a significant feature to isolate pin-to-pin cross-talk, with 50% improvement of the cross-talk isolation over the DaVinci 56 test socket. DaVinci 112 test socket increases production yields and throughput, eliminating false faults and complete functional failures. As a result, it has significantly improved our client’s chip test yields and overall test throughput while saving test costs.
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