EPC23101 – ePower™ Chipset eGaN® FET DATASHEET
●General Description
■The EPC23101 ePower™ IC integrates a half-bridge gate driver with an internal high side FET. It is designed as part of a chipset with a companion low side eGaN® FET such as the EPC2302. Integration is implemented using EPC's proprietary GaN IC technology. The high side monolithic chip integrates input logic interface, level shifting, bootstrap charging and gate drive buffer circuits along with a high side eGaN output FET. The low side output FET is driven by the gate driver output of the GaN IC to configure a half-bridge power stage.
■The on-chip gate drive buffers practically eliminate effects of common source inductance and gate drive loop inductance. Power loop inductance is minimized by compatible high side to low side pinout configuration that facilitates optimal layout technique. Switching times are tuned by external resistors to achieve 1–3 ns rise and fall times from 0–48 V at full load current. Over-voltage spikes can be controlled to less than +10 V above rail and –10 V below ground during hard switching transitions by choosing the tuning resistors, RBOOT and RDRV.
■The EPC23101 IC only requires an external 5 V VDRV power supply. Internal low side and high side power supplies, VDD and VBOOT, are generated from the external supply via a series connected switch. The internal supplies can be cut off to save quiescent power by turning off the switch with 5 V applied to the EN pin.
■The charging path for the floating bootstrap supply is activated with LSIN logic. It uses eGaN FET as the series switch that minimizes power losses by eliminating reverse recovery. This synchronous bootstrap charging circuit also minimizes voltage drop in the charging path.
■Robust level shifters from low side to high side channels are designed to operate correctly even at large negative clamped voltage and to avoid false trigger from fast dv/dt transients including those driven by external sources or other phases.
■Protection is provided by high side and low side under-voltage lockout to keep both FETs off at low supply voltages. If the supply voltages drop even lower or are lost while VIN is active at greater than 10 V, another active pull-down circuit is used with biasing from VIN to prevent destructive turn-on of both FETs from gate to drain leakage.
■The EPC23101 IC is capable of interfacing to digital controllers that use standard 3.3 V or 5 V CMOS logic levels. Separate and independent high side and low side logic control inputs allow external controllers to set fixed or adaptive dead times for optimal operating efficiency. Cross conduction prevention logic keeps both FETs off when logic inputs are both high at the same time.
■The FET gate drive voltages are derived from the internal low side and high side power supplies. Full gate drive voltages are only available after the HSIN and LSIN PWM inputs start to operate for a few cycles.
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[ Buck Converters ][ Boost Converters ][ Half-Bridge Converters ][ Full Bridge Converters ][ LLC Converters ][ Motor Drive Inverter ] |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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December, 2022 |
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1.5 MB |
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